1. Field of the Invention PA0 2. Description of the Prior Art PA0 1. General Object PA0 2. First Class of Specific Objects--High Performance Physical Layout and Interconnection PA0 3. Second Class of Specific Objects--High Level Functionality PA0 4. Third Class of Specific Objects--Versatile Configurability PA0 5. Fourth Class of Specific Objects--Time-Phased Distributed Arbitration PA0 6. Fifth Class of Specific Objects--Pipelining and Pin Multiplexing PA0 7. Sixth Class of Specific Objects--Error Detection PA0 8. Seventh Class of Specific Objects--Error Compensation PA0 1. General Overview of the Invention PA0 2. The Versatile Bus Design Considerations and Resultant Definition PA0 3. Transaction Level Functioning of the Versatile Bus PA0 4. Sample Applications of the Versatile Bus PA0 5. Interconnection of Multiple Versatile Buses PA0 6. The Versatile Bus Interface Logics to User Interface PA0 7. The Versatile Bus Interface Logics to VM Node Interface PA0 8. VLSIC Standard Cells From Which the Versatile Bus Is Built PA0 9. Description of the Versatile Bus Interface Logics PA0 10. Modifications and Variations to the Preferred Embodiment of the Invention PA0 11. Versatile Bus Configurations Supported by the Preferred Embodiment of the Invention. PA0 12. Scan/Set Test Loops.
2.1. Bus Topology and Performance PA1 2.2. Bus Variability PA1 2.3. Requirements for a VLSIC Standard Interconnect and Pinout Problem PA1 2.4. Interconnect Efficiency PA1 2.5. Prior Art Error Detection and Correction PA1 2.6. Prior Art VLSI Wire-OR Interconnection PA1 1.1. Philosophy of the Invention PA1 1.2. Configuration of the Versatile Busy by Interconnection Primitives PA1 1.3. Functional Interfaces of the Versatile Bus PA1 1.4. Distributed, Time-Phased, Selectable Priority Arbitration PA1 1.5. Pin Multiplexed or Pipelined Operations PA1 1.6. Versatile Bus Logics Interface to User PA1 1.7. VLSI Wired-OR Logic and Two Phase Electrical Communication Protocol PA1 1.8. Error Detection and Ripple Switched Error Compensation PA1 1.9. Versatile Bus Logics Interface to VM Node for Initializing and Maintenance PA1 1.10. Parity Generation/Detection Logic Circuit from Transfer Gates PA1 1.11. Performance Summary of the Versatile Bus PA1 2.1. Versatile Bus Design Definition at the First, Electrical Level PA1 2.2. Versatile Bus Design Definition at the Second, Topological Level PA1 3.1. Sequencing of Transaction Activities PA1 3.2. Arbitration PA1 3.3. Slave Identification/Function PA1 3.4. Wait PA1 3.5. Data PA1 3.6. Activity Multiplexing PA1 3.7. Error Control PA1 3.8. Number of Configuration PA1 3.9. Manner of Configuring PA1 3.10. Timing of Versatile Bus Activity PA1 4.1. Sample Memory Operations PA1 4.2. Sample Versatile Bus Configurations for Interfacing Requestors with Memory PA1 5.1. Basic Approach PA1 5.2. Application Areas PA1 5.3. Examples of Versatile Bus Transceiver Use PA1 5.4. Fault Tolerant Systems PA1 6.1. The Versatile Bus Interface Logics to User Interface for a Normal Transaction Upon the Versatile Bus PA1 6.2. Versatile Bus Interface Logics to User Interface During Block Data Transfer PA1 6.3. Versatile Bus Interface Logics to User Interface for Storing Slave Indentification Codes and a Mask Quantity PA1 6.4. Versatile Bus Interface Logics to User Interface for the Configuration of No Arbitration and No Slave Indentification/Function Upon the Versatile Bus PA1 6.5. Versatile Bus Interface Logics to User Interface for the Special Operation of Cancelling a Pending Transaction PA1 7.1. Interface Signals Between the Versatile Bus Interface Logics and the VM Node/Maintenance Processor PA1 7.2. Versatile Bus Interface Logics to VM Node/Maintenance Processor Interface for Initialization of a Versatile Bus System PA1 8.1. AND-OR INVERT 2-1 Logical Element PA1 8.2. AND-OR-INVERT 2-2 Logical Element PA1 8.3. AND-OR-INVERT 2-1-1 Logical Element PA1 8.4. AND-OR-INVERT 2-2-2 Logical Element PA1 8.5. INVERTOR Logical Element PA1 8.6. NEGATIVE AND-2 Input Logical Element PA1 8.7. NEGATIVE OR-2 Input Logical Element PA1 8.8. NEGATIVE AND-3 Input Logical Element PA1 8.9. NEGATIVE OR-3 Input Logical Element PA1 8.10. NEGATIVE AND-4 Input Logical Element PA1 8.11. NEGATIVE OR-4 Input Logical Element PA1 8.12. NEGATIVE AND-8 Input Logical Element PA1 8.13. SELECTOR-SINGLE 1 OF 2 Logical Element PA1 8.14. The CMOS Transfer GAte PA1 8.15. SELECTOR--Single 1 OF 4 Element PA1 8.16. 1 OF 2 SELECTOR--8 WIDE Logical Element PA1 8.17. 1 OF 2 SELECTOR WITH TEST--8 WIDE Logical Element PA1 8.18. 1 OF 4 SELECTOR--8 WIDE Logical Element PA1 8.19. 1 OF 4 SELECTOR WITH TEST--8 WIDE Logical Element PA1 8.20. BINARY SHIFT MATRIX Logical Element PA1 8.21. MINUS ONE SUBTRACTOR Logical Element PA1 8.22. MASKED COMPARATOR--8 WIDE Logical Element PA1 8.23. HOLDING REGISTER--8 WIDE MASTER Logical Element PA1 8.24. HOLDING REGISTER--8 WIDE SLAVE Logical Element PA1 8.25. DRIVER/RECEIVER Logical Element PA1 9.1. Block Diagram of the Versatile Bus Interface Logics PA1 9.2. Receive Control PA1 9.3. Send Control PA1 9.4. Arbitration Section PA1 9.5. Input Master ID Encoder Functional Subsection PA1 9.6. Group Count and Shift PA1 9.7. Master ID PA1 9.8. One Line per Group and Two Line per Group Decoders PA1 9.9. 3 Bit Generator and 3 to 8 Decoder PA1 9.10. Encoded Group Line Selector PA1 9.11. Group Line Output PA1 9.12. Group Line Output Gates PA1 9.13. Mask Register PA1 9.14. Mask Generator PA1 9.15. Mask Enable Generator PA1 9.16. Group Line Input Encoders PA1 9.17. Test Selector PA1 9.18. 36 Bit Group Line Memory PA1 9.19. Input Master ID Selector PA1 9.20. Winner's Master ID Register PA1 9.21. CAM and WAIT Block Diagram PA1 9.22. CAM and WAIT Control PA1 9.23. Slave Identification/Function Input Control PA1 9.24. Slave ID Section PA1 9.25. Receive Counter Control PA1 9.26. Busy Section PA1 9.27. Data Section PA1 9.28. Configuration Register PA1 9.29. Configuration Translation PA1 9.30. Driver/Receivers PA1 9.31. Parity Generation and Fault Detection PA1 9.33. Clear Distribution PA1 9.34. Clock Distribution PA1 9.35. Test Signal Distribution PA1 9.36. Scan/Set Loop Data PA1 9.37. Scan/Set Loop Control
2.2.1. Fundamental Interconnect Requirements PA2 2.2.2. Parameters of Variation PA2 2.2.3. Prior Art Standards of Interconnect PA2 2.1.1. Data Transfer Rate PA2 2.1.2. Fanout Capacity PA2 2.1.3. Wired-OR PA2 2.1.4. Collisions PA2 2.1.5. Power Off PA2 2.2.1. Interconnection PA2 2.2.2. Multiple Interconnection PA2 2.2.3. Synchronization PA2 2.2.4. Bit Sliced Interconnect PA2 2.2.5. Error Detection and Correction PA2 3.2.1. Arbitration Groups and Arbitration Lines PA2 3.2.2. The Default Winner PA2 3.2.3. Multiple Arbitration Groups PA2 3.2.4. Time-phased Arbitration PA2 3.2.5. Arbitration Configuration Parameters PA2 3.9.1. The Configuration of Arbitration PA2 3.9.2. Configuration for Slave Identification/Function PA2 3.9.3. Configuration for Wait PA2 3.9.4. Configuration for Data Transfer PA2 3.9.5. Configuration for Pin Multiplexing PA2 3.9.6. Pin (Line) Utilization of Configurations PA2 3.10.1. Timing of Multiplexed and Pipelined Transactions PA2 3.10.2. Timing of a Pipelined Versatile Bus Conducting Multiple Cycles of Time-Phased Arbitration PA2 3.10.3. Versatile Bus Timing with Activities of Multiple Cycles PA2 3.10.4. Timing of Versatile Buses with Null Activities PA2 3.10.5. Timing of Block Data Transfers PA2 3.10.6. Versatile Bus Timing and Pin Utilization PA2 4.2.1. Sample Versatile Bus Configurations for Communication with a Fast Memory PA2 4.2.2. Sample Versatile Bus Configurations for Communication with a Large Memory PA2 5.2.1. Interconnection of Different Versatile Buses PA2 5.2.2. Bidirectional Interconnect PA2 5.2.3. Interconnection of Differently Configured Versatile Buses PA2 5.2.4. Bit Sliced Systems PA2 5.3.1. The Matrix Swiltch Interface PA2 5.3.2. Single Scale Integrated Circuit Compatible Interfaces PA2 5.4.1. Redundant Devices Upon the Versatile Bus PA2 9.3.1. General Explanation of Send Control PA2 9.3.2. Generation of Signal TRANSACTION ENABLE PA2 9.3.3. Initialization of the Versatile Bus Interface Logics PA2 9.3.4. Initiate Transaction PA2 9.3.5. Termination of Arbitration and Capture of the Winner's Master Arbitration Identification Code PA2 9.3.6. Initialization and Shift Control of the Arbitration Group Counter PA2 9.3.7. Arbitration Won/Lost Latches PA2 9.3.8. Arbitration in Process Latches PA2 9.3.9. Initiation of Slave Identification/Function PA2 9.3.10. Slave Identification/Function in Process Latches PA2 9.3.11. Wait in Process Latch PA2 9.3.12. Data in Process Latches PA2 9.3.13. Strobing Data and Transaction Completed PA2 9.4.1. Master ID Subsection PA2 9.4.2. Code Generator and Decoders PA2 9.4.3. Group Line Output Subsection PA2 9.4.4. Arbitration Drive of the Versatile Bus PA2 9.4.5. Receipt of Arbitration into Priority Logic PA2 9.4.6. Mask Subsection and Group Count and Shift Subsection PA2 9.4.7. Mask Enable Generator and Mask Generator PA2 9.4.8. Winning or Losing Arbitration PA2 9.4.9. Input Master ID Encoder PA2 9.4.10. Input Master ID Selector and Winner's Master ID Subsection PA2 9.5.1. Group Line Input Encoder and Selectors Block Diagrams PA2 9.5.2. Test Selector PA2 9.5.3. 36 Bit Group Line Memory PA2 9.25.1. ARB and SID Cycle Counter Control PA2 9.25.2. Data Cycle Counter Control PA2 9.25.3. Cycle Counters PA2 9.26.1. Busy In Counter Control PA2 9.26.2. Busy In Counter PA2 9.26.3. Busy Enable PA2 9.26.4. Slave Identification/Function Busy Counter PA2 9.26.5. Data Busy Counter Control PA2 9.26.6. Data Busy Counter PA2 9.26.7. Word Count Multiplier PA2 9.27.1 Data Output Selector PA2 9.30.1. Driver/Receivers--Part A--Data Flow PA2 9.30.2. Driver/Receivers--Part B--Driver Clock and Faults PA2 9.30.3. Driver/Receivers--Part C--Clock and Test PA2 9.32. Fault Register